Hi,
For everyone that are working at the port of WebServer Demo for STR91x using GCC, please help me! I need the startup files (.s, .ld) for this board. I try to used the official file supplied by ST and modified by Raisonance but with these file the board don't start.If anyone have these files, please send me by email: fabrizio.tortis@email.it.

Thanks!

Can you post the file you are trying to use?

Hi,
This is crt0.s:
.extern main


;/* the following are useful for initializing the .data section */
.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata ;/* start address for the .data section. defined in linker script */
.extern _edata ;/* end address for the .data section. defined in linker script */

;/* the following are useful for initializing the .bss section */
.extern _sbss ;/* start address for the .bss section. defined in linker script */
.extern _ebss ;/* end address for the .bss section. defined in linker script */

;/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set Mode_FIQ, 0x11 ;/* FIQ Mode */
.set Mode_IRQ, 0x12 ;/* IRQ Mode */
.set Mode_SVC, 0x13 ;/* Supervisor Mode */
.set Mode_ABT, 0x17 ;/* Abort Mode */
.set Mode_UNDEF, 0x1B ;/* Undefined Mode */
.set Mode_SYS, 0x1F ;/* System Mode */

.extern VIC0_BASE
.extern VIC1_BASE
;/*.set VectorAddress VIC0_BASE ; /*VIC Vector address register address.*/
;/*.set VectorAddressDaisy VIC1_BASE ; /*Daisy VIC Vector address register*/


.equ I_Bit, 0x80 ;/* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 ;/* when F bit is set, FIQ is disabled */

/*; --- System memory locations */

;/* init value for the stack pointer. defined in linker script */
.extern _estack

;/* Stack Sizes. The default values are in the linker script, but they can be overriden. */
.extern _SVC_Stack_Init
.extern _ABT_Stack_Init
.extern _FIQ_Stack_Init
.extern _IRQ_Stack_Init


.extern _UND_Stack_Size
.extern _SVC_Stack_Size
.extern _ABT_Stack_Size
.extern _FIQ_Stack_Size
.extern _IRQ_Stack_Size
.extern _USR_Stack_Size

SVC_Stack = _SVC_Stack_Init /*_estack*/ /*;
/*; top of memory */

IRQ_Stack = _IRQ_Stack_Init /*SVC_Stack - 256*/ /*; followed by IRQ stack */
FIQ_Stack = _FIQ_Stack_Init /*USR_Stack-1024*/ /*; followed by FIQ stack*/
ABT_Stack = _ABT_Stack_Init /*FIQ_Stack-256*/ /*; followed by ABT stack */

/*; STR9X register specific definition*/

.equ SCRO_AHB_UNB, 0x5C002034

/***************************************************************************************/



/*;*******************************************************************************
;* Macro Name : SaveContext
;* Description : This macro used to save the context before entering
; an exception handler.
;* Input : The range of registers to store.
;* Output : none
;*******************************************************************************/

.macro Savecontext $r0,$r12
STMFD sp!,{r0-r12,lr}
MRS r1,spsr
STMFD sp!,{r1}
.endm
/*;*******************************************************************************
;* Macro Name : RestoreContext
;* Description : This macro used to restore the context to return from
; an exception handler and continue the program execution.
;* Input : The range of registers to restore.
;* Output : none
;*******************************************************************************/
.macro RestoreContext $r0,$r12
LDMFD sp!,{r1} /*; Restore the saved spsr_mode into r1.*/
msr spsr_cxsf,r1 /*; Restore spsr_mode.*/
LDMFD sp!,{r0-r12,pc}^ /*; Return to the instruction following...*/
.endm /*; ...the exception interrupt.*/


/*.section .text0*/
.section .flashtext
.globl _start
.globl _startup

/*.text*/
_startup:
_start:

ldr PC, Reset_Addr
ldr PC, Undefined_Addr
ldr PC, SWI_Addr
ldr PC, Prefetch_Addr
ldr PC, Abort_Addr
nop /*; Reserved vector*/
ldr PC, IRQ_Addr
/*ldr PC, FIQ_Addr*/


/*;*******************************************************************************
;* Function Name : FIQHandler
;* Description : This function is called when FIQ
; exception is entered.
;* Input : none
;* Output : none
;******************************************************************************* */

FIQHandler:
SUB lr,lr,#4 /*; Update the link register.*/
SaveContext r0,r7 /* ; Save the workspace plus the current*/
/*; return address lr_ fiq and spsr_fiq.*/
BL FIQ_Handler /*; Branch to FIQ_Handler.*/
RestoreContext r0,r7 /*; Restore the context and return to the...*/
/*; ...program execution.*/




Reset_Addr : .long Reset_Handler
Undefined_Addr : .long UndefinedHandler
SWI_Addr : .long SWIHandler
Prefetch_Addr : .long PrefetchAbortHandler
Abort_Addr : .long DataAbortHandler
.long 0 /*; Reserved vector*/
IRQ_Addr : .long IRQHandler
/*FIQ_Addr : .long FIQHandler*/


/*;*******************************************************************************
;* Function Name : UndefinedHandler
;* Description : This function called when undefined instruction
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

UndefinedHandler:
SaveContext r0,r12 /*; Save the workspace plus the current*/
BL Undefined_Handler/*; Branch to Undefined_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following..*/
/*; ...the undefined instruction.*/

/*;*******************************************************************************
;* Function Name : SWIHandler
;* Description : This function called when SWI instruction executed.
;* Input : none
;* Output : none
;*******************************************************************************/

SWIHandler:
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_ svc and spsr_svc.*/
BL SWI_Handler /*; Branch to SWI_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following...*/
/*; ...the SWI instruction.*/

/*;*******************************************************************************
;* Function Name : IRQHandler
;* Description : This function called when IRQ exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/


IRQHandler:
SUB lr,lr,#4 ; /*Update the link register*/
SaveContext r0,r12 ; /*Save the workspace plus the current*/
; /*return address lr_irq and spsr_irq*/
LDR r0, = VIC0_BASE
LDR r0, [r0] ; /*Read the routine address*/
LDR r1, = VIC1_BASE
LDR r1, [r1]
; /*Padding between the acknowledge and re-enable of interrupts*/
; /*For more details, please refer to the following URL*/
; /*http://www.arm.com/support/faqip/3682.html*/
NOP
NOP
MSR cpsr_c,#0x1F ; /*Switch to SYS mode and enable IRQ*/
STMFD sp!,{lr} ; /*Save the link register.*/
LDR lr, = IRQ_ReturnAddress ; /*Read the return address.*/
MOV pc, r0 ; /*Branch to the IRQ handler.*/
IRQ_ReturnAddress:
LDMFD sp!,{lr} ; /*Restore the link register.*/
MSR cpsr_c,#0xD2 | I_Bit ; /*Switch to IRQ mode and disable IRQ*/
LDR r0, = VIC0_BASE ; /*Write to the VectorAddress to clear the*/
STR r0, [r0] ; /*respective interrupt in the internal interrupt*/
LDR r1, = VIC1_BASE ; /*Write to the VectorAddressDaisy to clear the*/
STR r1,[r1] ; /*respective interrupt in the internal interrupt*/
RestoreContext r0,r12 ; /*Restore the context and return to the...*/
; /*...program execution.*/


/*;*******************************************************************************
;* Function Name : PrefetchAbortHandler
;* Description : This function called when Prefetch Abort
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

PrefetchAbortHandler:
SUB lr,lr,#4 /* ; Update the link register.*/
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_abt and spsr_abt.*/
BL Prefetch_Handler/*; Branch to Prefetch_Handler. */
RestoreContext r0,r12 /*; Return to the instruction following that... */
/*; ...has generated the prefetch abort exception.*/

/*;*******************************************************************************
;* Function Name : DataAbortHandler
;* Description : This function is called when Data Abort
; exception is entered.
;* Input : none
;* Output : none
;********************************************************************************/

DataAbortHandler:
SUB lr,lr,#8 /*; Update the link register.*/
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_ abt and spsr_abt.*/
BL Abort_Handler /*; Branch to Abort_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following that...*/
/*; ...has generated the data abort exception.*/

/*;*******************************************************************************
;* Macro Name : IRQ_to_SYS
;* Description : This macro used to switch form IRQ mode to SYS mode
;* Input : none.
;* Output : none
;*******************************************************************************/
.macro IRQ_to_SYS

MSR cpsr_c,#0x1F
STMFD sp!,{lr}
.endm
/*;*******************************************************************************
;* Macro Name : SYS_to_IRQ
;* Description : This macro used to switch from SYS mode to IRQ mode
; then to return to IRQHnadler routine.
;* Input : none.
;* Output : none.
;*******************************************************************************/
.macro SYS_to_IRQ
LDMFD sp!,{lr} /*; Restore the link register. */
MSR cpsr_c,#0xD2 /*; Switch to IRQ mode.*/
MOV pc,lr /*; Return to IRQHandler routine to clear the*/
/*; pending bit.*/
.endm


/***********************************************************************************************/
Reset_Handler:
ldr PC, =NextInst

NextInst:

nop
nop
nop
nop
nop
nop
nop
nop
nop

/*; --- ARM9 core configuration*/

Enable_SRAM_96K:
ldr R0, =SCRO_AHB_UNB
ldr R1, =0x0196 /*TODO: the value written there should depend on the derivative...*/
str R1, [R0]

MRC P15,0,r0,c1,c0,0

/*; Initialize Stack pointer for various CPU Modes.*/


MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
LDR SP, =ABT_Stack

MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
LDR SP, =_estack /*RAM_Limit*/

msr CPSR_c, #Mode_FIQ /*; Change to FIQ mode*/
ldr SP, =FIQ_Stack /*; Initialize FIQ stack pointer */

msr CPSR_c, #Mode_IRQ /*; Change to IRQ mode */
ldr SP, =IRQ_Stack /*; Initialize IRQ stack pointer*/
msr CPSR_c, #Mode_SYS /* ; Change to System mode*/

/*IMPORT __main */

;/* copy the initial values for .data section from FLASH to RAM */
ldrR1, =_sidata
ldrR2, =_sdata
ldrR3, =_edata
_reset_inidata_loop:
cmpR2, R3
ldrlOR0, [R1], #4
strlOR0, [R2], #4
blO_reset_inidata_loop

;/* Clear the .bss section */
mov r0,#0;/* get a zero */
ldr r1,=_sbss;/* point to bss start */
ldr r2,=_ebss;/* point to bss end */
_reset_inibss_loop:
cmp r1,r2;/* check if some data remains to clear */
strlo r0,[r1],#4;/* clear 4 bytes */
blo _reset_inibss_loop;/* loop until done */




/************************************************************************************************/


/*; --- Now enter the C code */
ldr PC, ___main
___main : .long main

/*b main */ /*; Note : use B not BL, because an application will
/*; never return this way*/







/*LTORG


END
;*************
****** (C) COPYRIGHT 2003 STMicroelectronics *****
****** (C) COPYRIGHT 2005 RAISONANCE *****

END OF FILE****/

These are the 3 linker file:

STR91xFx44_Flash.ld:

/*
Default linker script for STR91xFx44
Copyright RAISONANCE S.A.S. 2006
*/

/* include the common STRxxx sub-script */
INCLUDE "STR91x_COMMON.ld"


/*********** BEGIN SUBSCRIPT ************/

/*
Linker subscript for STR91xFx44 definitions
Copyright RAISONANCE 2006
You can use, modify and distribute this file freely, but without any warranty.
*/


/* Memory Spaces Definitions */

MEMORY
{
FLASH (rx) : ORIGIN = 0, LENGTH = 512K
FLASHB1 (rx) : ORIGIN = 0x00400000, LENGTH = 32K
EXTMEMB0 (rx) : ORIGIN = 0x30000000, LENGTH = 64M
EXTMEMB1 (rx) : ORIGIN = 0x34000000, LENGTH = 64M
EXTMEMB2 (rx) : ORIGIN = 0x38000000, LENGTH = 64M
EXTMEMB3 (rx) : ORIGIN = 0x3C000000, LENGTH = 64M
RAM (xrw) : ORIGIN = 0x50000000, LENGTH = 96K
}

/* higher address of the user mode stack */
_estack = 0x50004000;

/************ END SUBSCRIPT *************/

/* include the sections management sub-script for FLASH mode */
INCLUDE "sections_FLASH.ld"

SECTION_FLASH.ld:

/*
Common part of the linker scripts for STR71x devices in FLASH mode
(that is, the FLASH is seen at 0)
Copyright RAISONANCE 2005
You can use, modify and distribute thisfile freely, but without any waranty.
*/



/* Sections Definitions */

SECTIONS
{
/* the beginning of the startup code is stored in the .flashtext section */
.flashtext :
{
. = ALIGN(4);

crt0*.o (.flashtext) /* Startup code */
crt0*.o (.text) /* Startup code */
*crt0*.o (.flashtext) /* Startup code */
*crt0*.o (.text) /* Startup code */
*startup.o (.flashtext) /* Startup code */
*(.flashtext) /* Startup code */
*(.text0) /* Startup code */
. = ALIGN(4);
} >FLASH


/* the program code is stored in the .text section */
.text :
{
. = ALIGN(4);

/**crt0*.o (.text)*/ /* Startup code */
/**startup.o (.text)*/ /* Startup code */
*(.text) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)

. = ALIGN(4);
_etext = .;
/* This is used by the startup in order to initialize the .data secion */
_sidata = _etext;
} >FLASH



/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data : AT ( _sidata )
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;

*(.data)

. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM



/* This is the uninitialized data section */
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;

*(.bss)
*(COMMON)

. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} >RAM

PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );

/* This is the user stack section
This is just to check that there is enough RAM left for the User mode stack
It should generate an error if it's full.
*/
._usrstack :
{
. = ALIGN(4);
_susrstack = . ;

. = . + _Minimum_Stack_Size ;

. = ALIGN(4);
_eusrstack = . ;
} >RAM



/* this is the FLASH Bank1 */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
.b1text :
{
*(.b1text) /* remaining code */
*(.b1rodata) /* read-only data (constants) */
*(.b1rodata*)
} >FLASHB1

/* this is the EXTMEM */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */

/* EXTMEM Bank0 */
.eb0text :
{
*(.eb0text) /* remaining code */
*(.eb0rodata) /* read-only data (constants) */
*(.eb0rodata*)
} >EXTMEMB0

/* EXTMEM Bank1 */
.eb1text :
{
*(.eb1text) /* remaining code */
*(.eb1rodata) /* read-only data (constants) */
*(.eb1rodata*)
} >EXTMEMB1

/* EXTMEM Bank2 */
.eb2text :
{
*(.eb2text) /* remaining code */
*(.eb2rodata) /* read-only data (constants) */
*(.eb2rodata*)
} >EXTMEMB2

/* EXTMEM Bank0 */
.eb3text :
{
*(.eb3text) /* remaining code */
*(.eb3rodata) /* read-only data (constants) */
*(.eb3rodata*)
} >EXTMEMB3



/* after that it's only debugging information. */

/* remove the debugging information from the standard libraries */
DISCARD :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}

/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

STR91x_COMMON:

/*
Common part of the linker scripts for STR91x devices
Copyright RAISONANCE 2006
You can use, modify and distribute thisfile freely, but without any waranty.
*/


/* Registers mapping */


EXTMEM_BASE = 0x30000000 ;
APB0_BASE = 0x58000000 ;
APB1_BASE = 0x5C000000 ;
FMI_BASE = 0x54000000 ;

USB_BASE = 0x70000000 ;

VIC0_BASE = 0xFC000000 ;
VIC1_BASE = 0xFFFFF000 ;


PROVIDE( _VIC0 = (VIC0_BASE) );
PROVIDE( _VIC1 = (VIC1_BASE) );

PROVIDE( _USB = (USB_BASE) );

PROVIDE( _AHBAPB0 = (APB0_BASE) );
PROVIDE( _WIU = (APB0_BASE + 0x1000) );
PROVIDE( _TIM0 = (APB0_BASE + 0x2000) );
PROVIDE( _TIM1 = (APB0_BASE + 0x3000) );
PROVIDE( _TIM2 = (APB0_BASE + 0x4000) );
PROVIDE( _TIM3 = (APB0_BASE + 0x5000) );
PROVIDE( _GPIO0 = (APB0_BASE + 0x6000) );
PROVIDE( _GPIO1 = (APB0_BASE + 0x7000) );
PROVIDE( _GPIO2 = (APB0_BASE + 0x8000) );
PROVIDE( _GPIO3 = (APB0_BASE + 0x9000) );
PROVIDE( _GPIO4 = (APB0_BASE + 0xA000) );
PROVIDE( _GPIO5 = (APB0_BASE + 0xB000) );
PROVIDE( _GPIO6 = (APB0_BASE + 0xC000) );
PROVIDE( _GPIO7 = (APB0_BASE + 0xD000) );
PROVIDE( _GPIO8 = (APB0_BASE + 0xE000) );
PROVIDE( _GPIO9 = (APB0_BASE + 0xF000) );

PROVIDE( _AHBAPB1 = (APB1_BASE) );
PROVIDE( _RTC = (APB1_BASE + 0x1000) );
PROVIDE( _SCU = (APB1_BASE + 0x2000) );
PROVIDE( _SPI0 = (APB1_BASE + 0x7000) );
PROVIDE( _SPI1 = (APB1_BASE + 0x8000) );
PROVIDE( _CAN = (APB1_BASE + 0x9000) );
PROVIDE( _ADC = (APB1_BASE + 0xA000) );






/* default stack sizes.

These are used by the startup in order to allocate stacks for the different modes.
*/

__SVC_Stack_Size = 256 ;
__IRQ_Stack_Size = 1024 ;
__USR_Stack_Size = 1024 ;
__FIQ_Stack_Size = 64 ;
__ABT_Stack_Size = 64 ;
__UND_Stack_Size = 64 ;

__SVC_Stack_Init = _estack ;
__IRQ_Stack_Init = __SVC_Stack_Init - __SVC_Stack_Size ;
__FIQ_Stack_Init = __IRQ_Stack_Init - __USR_Stack_Size ;
__ABT_Stack_Init = __FIQ_Stack_Init - __FIQ_Stack_Size ;
__UND_Stack_Init = __ABT_Stack_Init - __ABT_Stack_Size ;

/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
PROVIDE ( _SVC_Stack_Init = __SVC_Stack_Init ) ;
PROVIDE ( _IRQ_Stack_Init = __IRQ_Stack_Init ) ;
PROVIDE ( _FIQ_Stack_Init = __FIQ_Stack_Init ) ;
PROVIDE ( _ABT_Stack_Init = __ABT_Stack_Init ) ;
PROVIDE ( _UND_Stack_Init = __UND_Stack_Init ) ;

/*
the user mode stack is an exception because we want it at the end of the RAM.
therefore, we just check against a minimum.
The value below is the minimum memory required for ALL THE STACKS.
There will be a link error if there is not this amount of RAM free at the end.
*/
_Minimum_Stack_Size = 0xC00 ;



/* default ISR addresses.

The startup needs these addresses defined from another object file.
In case they are not, these PROVIDEs redirect them to the Reset.

_start must be defined, usually in the startup.
*/

PROVIDE( Undefined_Handler = _start );
PROVIDE( SWI_Handler = _start );
PROVIDE( Prefetch_Handler = _start );
PROVIDE( Abort_Handler = _start );
PROVIDE( FIQ_Handler = _start );
PROVIDE( T0TIMI_IRQHandler = _start );
PROVIDE( FLASH_IRQHandler = _start );
PROVIDE( RCCU_IRQHandler = _start );
PROVIDE( RTC_IRQHandler = _start );
PROVIDE( WDG_IRQHandler = _start );
PROVIDE( XTI_IRQHandler = _start );
PROVIDE( USBHP_IRQHandler = _start );
PROVIDE( I2C0ITERR_IRQHandler = _start );
PROVIDE( I2C1ITERR_IRQHandler = _start );
PROVIDE( BSPI0_IRQHandler = _start );
PROVIDE( BSPI1_IRQHandler = _start );
PROVIDE( I2C0_IRQHandler = _start );
PROVIDE( I2C1_IRQHandler = _start );
PROVIDE( CAN_IRQHandler = _start );
PROVIDE( ADC12_IRQHandler = _start );
PROVIDE( T1TIMI_IRQHandler = _start );
PROVIDE( T2TIMI_IRQHandler = _start );
PROVIDE( T3TIMI_IRQHandler = _start );
PROVIDE( HDLC_IRQHandler = _start );
PROVIDE( USBLP_IRQHandler = _start );
PROVIDE( T0TOI_IRQHandler = _start );
PROVIDE( T0OC1_IRQHandler = _start );
PROVIDE( T0OC2_IRQHandler = _start );

When i use these files to link with webserver demo
i obtain the file .elf but when i load it into the board, the board don't start. I think that it is a problem of memory address.

Thanks!

This code does not seem to contain the FreeRTOS SWI or IRQ handler. See the demo for the IAR compiler. It also seems to call main in system mode. It will not work because it does not contain the FreeRTOS code!